International Journal of Computational
Intelligence Research (IJCIR)
Volume 3, Number 1 (2007)
A configware approach for the implementation of a LVQ neural network
Dept. Computer Science & Engineering, Nagoya Institute of Technology, Nagoya-shi, Showa-ku, Gokiso-cho, 466–8555, Japan.
Heitor S. Lopes
Bioinformatics Lab., Federal University of Technology – Paraná, Av. 7 de setembro, 3165 80230-901
This paper describes a methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device, especially suited for applications requiring fast throughoutput. A special feature of the implementation is a combinatorial module for distance comparison that allows the execution of this important operation for a LVQ in just one clock cycle. The control code of the LVQ is described by a finite state machine and parametrically programmed in VHDL. The final neural network was implemented with 64 dimensions, 16 subclusters and 2 classes, using an ACEX1k100 reconfigurable device. Using this system with a clock rate of 25MHz, a full classification can be done in 334µs, thus enabling real-time performance for many real-world applications.
LVQ, FPGA, Hardware.